The present invention relates to integrated circuit (i.e., chip) manufacturing, and more specifically, to self-aligned double patterning-aware routing in chip manufacturing.
Self-aligned double patterning (SADP) is a relatively new chip manufacturing technology characterized by multiple and continuous track patterns for wires. While the wires are initially formed as continuous tracks, segments of the tracks must be removed, in accordance with the integrated circuit design and, specifically, the routing result, to create discontinuities in specified locations. A typical routed design indicates the locations of the wires. However, in view of the continuous wires associated with SADP, the router must also specify the placement of trim shapes that define the discontinuities in the wires. The trim shapes must be placed according to design rules that ensure that opens or shorts are not created. Thus, self-aligned double patterning-aware routing is needed in chip manufacturing.